# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI 10nm PHY

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

allOf:
  - $ref: dsi-phy-common.yaml#

properties:
  compatible:
    enum:
      - qcom,dsi-phy-10nm
      - qcom,dsi-phy-10nm-8998

  reg:
    items:
      - description: dsi phy register set
      - description: dsi phy lane register set
      - description: dsi pll register set

  reg-names:
    items:
      - const: dsi_phy
      - const: dsi_phy_lane
      - const: dsi_pll

  vdds-supply:
    description: |
      Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
      connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target

  qcom,phy-rescode-offset-top:
    $ref: /schemas/types.yaml#/definitions/int8-array
    maxItems: 5
    description:
      Integer array of offset for pull-up legs rescode for all five lanes.
      To offset the drive strength from the calibrated value in an increasing
      manner, -32 is the weakest and +31 is the strongest.
    items:
      minimum: -32
      maximum: 31

  qcom,phy-rescode-offset-bot:
    $ref: /schemas/types.yaml#/definitions/int8-array
    maxItems: 5
    description:
      Integer array of offset for pull-down legs rescode for all five lanes.
      To offset the drive strength from the calibrated value in a decreasing
      manner, -32 is the weakest and +31 is the strongest.
    items:
      minimum: -32
      maximum: 31

  qcom,phy-drive-ldo-level:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description:
      The PHY LDO has an amplitude tuning feature to adjust the LDO output
      for the HSTX drive. Use supported levels (mV) to offset the drive level
      from the default value.
    enum: [ 375, 400, 425, 450, 475, 500 ]

required:
  - compatible
  - reg
  - reg-names

unevaluatedProperties: false

examples:
  - |
     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     #include <dt-bindings/clock/qcom,rpmh.h>

     dsi-phy@ae94400 {
         compatible = "qcom,dsi-phy-10nm";
         reg = <0x0ae94400 0x200>,
               <0x0ae94600 0x280>,
               <0x0ae94a00 0x1e0>;
         reg-names = "dsi_phy",
                     "dsi_phy_lane",
                     "dsi_pll";

         #clock-cells = <1>;
         #phy-cells = <0>;

         vdds-supply = <&vdda_mipi_dsi0_pll>;
         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                  <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "iface", "ref";

         qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
         qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
         qcom,phy-drive-ldo-level = <400>;
     };
...
